1. Field of the Invention
The present invention relates to a technique for operating a PLL (phase-locked loop) circuit at a high speed with a low power source voltage.
Priority is claimed on Japanese Patent Application No. 2007-042229, filed Feb. 22, 2007, the contents of which are incorporated herein by reference.
2. Description of the Related Art
The PLL circuit has a function of multiplying the frequency of a clock signal, controlling the skew with respect to a clock signal, or the like, and thus is an important circuit used in a semiconductor integrated circuit or an electronic device. With the advance of a low power source voltage and a high-speed operation of recent electronic devices, the PLL circuit should also operate with a low power source voltage and at a high speed.
For example, such a low power source voltage and a high-speed operation have been possible with respect to a DRAM (dynamic random access memory), which causes a reduction of the margin provided for the operation of a PLL circuit, which is included in the DRAM so as to control the relevant parts of the DRAM.
As a PLL circuit coping with such a low power source voltage, Japanese Unexamined Patent Application, First Publication No. H08-130465 discloses a PLL circuit having a wide control-voltage range with respect to a charge pump circuit.
Generally, the charge pump circuit is a main circuit which restricts the low power source voltage and the high-speed operation.
FIG. 13 is a circuit diagram showing a charge pump circuit and a loop filter which are generally used in a PLL circuit. In a charge pump circuit 1100, a control voltage Vcont is (i) increased by outputting a current Iup to a loop filter 103 in accordance with an increase signal “UP” (i.e., signal for designating an increase in the control voltage), and (ii) decreased by receiving a current Idown from the loop filter 103 in accordance with a decrease signal “DOWN”.
Additionally, in the PLL circuit, a voltage-controlled oscillator (VCO) is connected to the control voltage Vcont so that the oscillation frequency of the VCO is controlled by the control voltage Vcont. Generally, in such a VCO, the higher the control voltage Vcont, the higher the oscillation frequency.
That is, the control voltage Vcont should be high so as to obtain a high oscillation frequency of the VCO. However, as a result, the voltage between the drain and the source (i.e., drain-source voltage Vds) of a PMOS transistor 1101, which forms the charge pump circuit 1100, should be low.
The operation of the charge pump circuit 11 in this process will be explained with reference to FIG. 14, which shows the dependency of the outflow current Iup (which flows by means of the PMOS transistor 1101) and the inflow current Idown (which flows by means of an NMOS transistor 1102) on the control voltage Vcont. As shown in FIG. 14, when the control voltage Vcont increases, the operating point of the PMOS transistor 1101 may shift from the point B, which belongs to a saturation area, to the point A, which belongs to a linear area (i.e., area 1200 which is close to the power source voltage VDD).
In the vicinity of the point B, when the control voltage Vcont varies, a small variation occurs in the outflow current Iup and the inflow current Idown. In contrast, in the vicinity of the point A, when the control voltage Vcont varies, there is a considerable variation in the outflow current Iup.
That is, in order that the VCO oscillates at a constant frequency, the control voltage Vcont varies depending on a variation in the temperature or other conditions with regard to the relevant processes, and the outflow current Iup considerably varies in accordance with the variation in the control voltage Vcont, thereby increasing the difference between the outflow current Iup and the inflow current Idown.
On the other hand, when decreasing the power source voltage VDD, the drain-source voltage Vds of the PMOS transistor 1101 (which forms the charge pump circuit) also decreases, similar to the above process. As a result, the PMOS transistor 1101 operates at the point A which belongs to the linear area, which also causes the above-described problem.
That is, when decreasing the power source voltage VDD by increasing the oscillation frequency of the PLL circuit, there occurs a difference between the values of the outflow current Iup and the inflow current Idown. In addition, there occurs a large variation in the outflow current Iup in accordance with a variation in the temperature or other process conditions. Therefore, even when the PLL circuit is locked, there occurs a phase difference between the signals output from the relevant phase comparator (i.e., the signals UP and DOWN), which causes a drift in the oscillation frequency of the VCO (i.e., depending on a variation in the temperature or other process conditions).